1. Field of the Invention
The present invention is related to a memory device, and more particularly, to a memory device having write and/or read assist function.
2. Description of the Prior Art
FIG. 1 is a prior art memory cell array 100. The memory cell array 100 includes a plurality of memory cells 102, a plurality of word lines 104, a plurality of pairs of bit lines 106 and bit line bars 108. Each word line 104 is coupled to corresponding memory cells 102 in the same row, and each pair of bit line 106 and bit line bar 108 is coupled to corresponding memory cells 102 in the same column.
In FIG. 1, a word line 1042 is at a high logic level and a pair of bit line 1062 and bit line bar 1082 is at inverse logic levels in order to write a select cell (active cell) 1022 of the memory cells 102 at a write cycle. Memory cells 1024 in the same row with the memory cell 1022 are half select cells, and memory cells 102 coupled to word lines 104 other than the word line 1042 are off cells.
FIG. 2 is a prior art diagram illustrating butterfly curves of a memory cell 102. Curve 202 indicates voltage transfer characteristic when the memory cell 1024 is half selected, namely, the word line 1042 is at the high logic level and the bit line 106 and bit line bar 108 coupled to the memory cell 1024 are also at the high logic level. Curve 204 indicates voltage transfer characteristic when the memory cell 102 is an off cell, namely, a word line 104 coupled to the memory cell 102 is at a low logic level. As shown in FIG. 2, static noise margin (SNM) 206 is smaller when the memory cell 1024 is half selected comparing with the condition when the memory cell 102 is the off cell.
Thus, how to increase SNM when the memory cell 102 is half selected while maintaining relatively good write margin for the selected cell 1022 is an issue worth exploring.